TEJ4M_Unit3

Altera FPGA (Field Programable Gate Array)
 * ==**Week**== || ==**Course Material**== || ==**Important Dates**== ||
 * [[image:wk16.jpg]] || * May 26-30
 * As last week keep working on your project
 * Provide a written outline of your project - what you are trying to accomplish and your plans on how you are going to solve the issue (and any potential difficulties) by **Thursday May 29**. || Outline of proposed project **Thursday May 29** ||
 * [[image:wk15.jpg]] || * May 19 - 23
 * Keep working on your project.
 * Any outstanding assignments should also be completed and handed in before you find you run out of time
 * An outline of your project should be put together by next week ||  ||
 * [[image:wk14.JPG]] || * May 12-16
 * Start experimenting with ideas for your project


 * You will be provided with a handout outlining the requirements needed in your report for your project, to be handed in by the end of the school year.
 * It will include ideas such as:
 * requirements to do project
 * issues that came up and how they were resolved.
 * If this project inspired you to follow this as a career what are the education options you would need to follow. || Quiz on Karnaugh maps ||
 * [[image:wk13.jpg]] || * May 5-9
 * Continue with work on VHDL code to get a stepper motor working.


 * Handout of Remaining course expectations have been handed out to you. Start considering a project you are hoping to do that fulfill some of those expectations. ||  ||
 * [[image:wk12.jpg]] || * Mon Apr 28 - Tues Apr 29
 * Finish up combination Lock lab


 * Wed Apr 30 - May 2
 * Using chapter 3 notes "Introduciton to VHDL design" Determine how to get the stepper Motor working using the Altera board. ||  ||
 * [[image:wk11.jpg]] || * Tues Apr 22
 * Combinations of Logic Gates - determine the truth table for Automobile Circuitry
 * Try to determine the gates required to build the logic determined
 * Wed Apr 23
 * Finding the simplified logic circuitry for the Automobile
 * Introducing Karnaugh maps
 * Thurs Apr 24
 * Worksheet on Karnaugh maps - practice questions
 * Friday Apr 25
 * Combination Lock lab. || Lab creation assignment due Thurs Apr 24 ||
 * [[image:wk10.JPG]] || * Mon Apr 14 - Thurs Apr 17
 * Lab creation assignment
 * Using the information from the Pulsed operation Logic gates and the tutorials on gates on the Altera board, create a lab on the Altera board that teaches the Pulsed operation but executes it on the Max 7000 chip on the Altera board.
 * Lab requires some background information (including negative logic), How to execute the lab so it can be replicated and a final conclusion describing what the outcome is and what you should have learnt.
 * Due Date Next week. TBD ||  ||
 * [[image:wk9.JPG]] || * Mon Apr 7
 * Work on Gates sheets and lab (exclude simulation and wave emulation)
 * Tues Apr 8
 * Take up Logic Circuits to Expression sheet
 * Take up Expression to Logic Circuits sheet
 * Wed Apr 9
 * Finish taking up Expression to Logic Circuits sheet
 * Went over simplifying Boolean Expressions with tables
 * Thurs Apr 10
 * Simplifying Boolean Expressions sheet (start you off)
 * Fri Apr 11
 * Finalize lab and hand in
 * Quiz on Logic Circuits, Expressions and Simplification || Quiz on Friday ||
 * [[image:wk8.JPG]] || * Mar 31 - Apr 1
 * Handout package of creating Boolean expressions from gates,combinations of gates (and visa versa). Manipulating the expressions using Boolean theorems and creating simpler solutions.

= =
 * Apr 2-4
 * Review of Finish outstanding work. || Lab write up due Wed Apr 2 ||
 * [[image:wk7.JPG]] || * Mar 24-28
 * Continue with the lab creation using the previous labs as a source of inspiration to produce the tutorial or instructional lab to understand how gates can use pulsed input to produce a particular output. ||  ||
 * [[image:wk6.JPG]] || Welcome back from March Break * Mar 17
 * Introduction to Altera UP2 board
 * Answer questions regarding microcontrollers
 * Using the Altera User Guide determine the inputs and outputs for the UP2
 * Start installation of Web Application
 * Mar 18
 * Labs #1 - 2 using the protoboards, become reacquainted with logic gates and their functions as well as truth tables.
 * Mar 19 - Mar20
 * Activity 2 using the Tutorial, make sure you can output "hi" and another word using the MAX II chip on the Altera Board
 * Mar 21
 * Given the labs "Activity 3.1 and 3.2" and Lab 3 - create a lab that uses gates and pulsed input to activate show how pulsed input can be used to "activate" or create a predicted output. ||  ||