W15_TEJ4M_Unit3




 * Unit 3 - Applying Logic **


 * ==Week== || ==Course Work== || ==Important Dates== ||
 * [[image:wk11.jpg]] || * Apr 20 - Apr 21
 * 1) Second half of Automobile circuitry handed out. Make sure to have this done for Friday as a hand in assignment. It must include showing your circuitry working on your Altera board.
 * Apr 22 - Apr 23
 * 1) Combination Lock - Solve the combination || Automobile circuitry done for Friday. ||
 * [[image:wk10.JPG]] || * Apr 13
 * 1) Logic Gate Quiz
 * 2) Logic Circuit design
 * Apr 15 - 16
 * 1) Continue with Logic Circuit design
 * 2) Pulsed operational Logic lab
 * Apr 17
 * 1) Took up Logic Circuit design
 * 2) Investigation in Automobile circuitry, || Karnaugh Maps quiz - Wednesday Apr. 22 ||
 * [[image:wk9.JPG]] || * Apr 6
 * EASTER MONDAY - No School
 * Apr 7 - 8
 * 1) Continue work on Altera
 * Apr 9
 * 1) Take up work on simplifying expressions
 * 2) Hand out - Working with Logical expressions
 * Apr 10
 * 1) Take up Logical expressions example
 * 2) Hand out on Karnaugh Maps || Quiz on Logic Gates Monday Apr 13 ||
 * [[image:wk8.JPG]] || * Mar 30 - Apr 2
 * 1) Implement Activty 2 on Altera
 * 2) Simplifying boolean expressions
 * 3) Activiy 3 on Altera handed out
 * Apr 3
 * GOOD FRIDAY - No School ||  ||
 * [[image:wk7.JPG]] || * Mar 23
 * 1) Extra day to try and get networking information finalized
 * Mar 24
 * 1) First assignment to get you oriented with Altera Board
 * Mar 25 & 26
 * 1) Logic Gate review
 * Mar 27
 * 1) Activity 2 on the altera ||   ||